1. Field of the Invention
The present invention generally relates to microelectronic circuits, and more particularly to a microelectronic circuit and device having metal-insulator-metal capacitors.
2. Description of the Related Art
In today""s dynamic random access memory (DRAM) environment, achieving high density is of the utmost concern. As the DRAM size continues to grow larger, its performance becomes a concern. Therefore, it is critical to improve the performance of the DRAM, especially for short-cycle, high-speed embedded DRAMs. In order to compete with the technological embodiments of static random access memories (SRAMs), there are many performance breakthroughs which must occur to the DRAMs. One such breakthrough is to further reduce the DRAM size. The size of a DRAM macro is about 10 to 15 times smaller than that of SRAM with the same capacity. Moreover, the smaller the size, the less the delay. Unlike conventional stand-alone DRAMs, the size of erasable DRAM (eDRAM) is more difficult to reduce, which increases the process cost.
A Metal-Insulator-Metal (MIM) capacitor is commonly used as a decoupling capacitor in semiconductors. An MIM capacitor includes a lower and an upper electrode made of conducting materials such as polysilicon, metals, or metal alloys. Also, sandwiched between the electrodes is a thin layer of dielectric such as silicon nitride, silicon oxynitride, silicon oxide, or high-k materials such as aluminum oxide, tantalum pentoxide, titanium dioxides, barium strontium titanate, etc.
MIM capacitors can be added as discrete components to a chip, and are usually added at the terminal metal layer. More advance versions of MIM capacitors can be integrated on a chip die, for example in-between various back-end-of-the-line levels where they can provide a more efficient decoupling function and have a smaller tendency to introduce external noise due to closer contacts to the silicon level of the transistor. Two conventional designs are shown in U.S. Pat. Nos. 5,903,493 and 6,198,617, the complete disclosures of which are herein incorporated by reference. In these devices the capacitor element is above the metal regions M1.
It has been recognized that as chip sizes continue to become smaller and smaller, there is a need to move from a conventional poly gate structure to a metal gate structure. (See for example, xe2x80x9cNew Paradigm of Silicon Technology,xe2x80x9d Tadahiro Ohmi, et al., Proceedings of the IEEE, Vol. 89, No. 3 March 2001, pp 394-412; xe2x80x9cDual-Metal Gate CMOS Technology with Ultrathin Silicon Nitride Gate Dielectric,xe2x80x9d Yee-Chia Yeo et al., IEEE Electron Device Letters, Vol. 22, No. 5, May 2001, pp 227-229; xe2x80x9cDual-Metal Gate Technology for Deep-Submicron CMOS Transistor,xe2x80x9d Qiang Lu, et al., IEEE 2000 Symposium on VLSI Technology Digest of Technical Papers, pp 72-73; U.S. Pat. No. 6,057,583 xe2x80x9cTransistor with Low Resistance Metal Source and Drain Vertically Displaced From the Channelxe2x80x9d issued to Gardner, et al.; U.S. Pat. No. 6,165,858 xe2x80x9cEnhanced Silicidation Formation for High Speed MOS Device by Junction Grading with Dual Implant Dopant Speciesxe2x80x9d issued to Gardner, et al.; U.S. Pat. No. 6,033,963 xe2x80x9cMethod of Formning a Metal Gate for CMOS Devices Using a Replacement Gate Processxe2x80x9d issued to Huang, et al.; U.S. Pat. No. 6,130,123 xe2x80x9cMethod for Making a Complementary Metal Gate Electrode Technologyxe2x80x9d issued to Liang, et al.; U.S. Pat. No. 6,049,114 xe2x80x9cSemiconductor Device Having a Metal Containing Layer Overlying a Gate Dielectricxe2x80x9d issued to Maiti, et al., the complete disclosures of which are herein incorporated by reference.
Moreover, depending on the circuit design, the choice of gate material can have a work function matching that of a P-type silicon or a N-type silicon structure, or a work function between a P-type and N-type structure, which is denoted as a mid-gap metal. Typical examples of these three groups of gate materials are Ni, TaN, RuO and MoN; Ru, Ta and TaSi; and W, respectively. Similar conducting materials can be used on the source and drain regions of the silicon thereby taking advantage of using one of these metal contacts as the lower electrode for an MIM capacitor, which can significantly reduce the physical space over the conventional poly gate electrodes and MIM capacitor combination.
Thus, there is a need for a new device which utilizes a metal contact as a dual electrode to the source/drain of the transistor and the lower electrode of a MIM capacitor. Moreover, there is a need for a new device which offers a much higher packing density, yet does not have the other problems associated with conventional transistor devices.
In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional transistor devices, the present invention has been devised, and it is an object of the present invention to provide a structure and method for fabricating microelectronic circuits having metal gates as well as metal contact capacitors. Another object of the present invention is to significantly reduce the processing costs of fabricating such devices by sharing processing steps and materials between the metal gates and metal capacitors. Yet another object of the present invention is to utilize the method by using high density DRAM.
In order to attain the objects suggested above, there is provided, according to one aspect of the invention an integrated circuit structure comprising a pair of capacitors, each having metal plates separated by an insulator, and metal gate semiconductor transistors electrically connected to the capacitors. The metal gate of the transistors and one of the metal plates of each of the capacitors comprise the same metal level in the integrated circuit structure. More specifically, each of the capacitors comprises a vertical capacitor having an upper metal plate vertically over a lower metal plate and each metal gate of the transistors and each upper metal plate of the capacitors comprise the same metal level in the integrated circuit structure. Further, each of the transistors includes a drain region connected to a respective lower metal plate of an adjacent capacitor.
The invention also provides a method of forming a metal-insulator-metal capacitor and an associated semiconductor transistor having a metal gate. The method patterns sacrificial gate structures over a substrate, forms sidewall spacers adjacent the sacrificial gate structures, forms a first metal layer adjacent the sidewall spacers, planarizes the first metal layer, removes the sacrificial gate structures, forms an insulator over the first metal layer, removes a portion of the first metal layer from a gate region, and forms a second metal layer over the insulator and in the gate region. The second metal layer comprises both the gate of the transistor and a plate of the transistor.
The planarizing of the first metal layer reduces voids and surface irregularities in the second metal layer. The insulator comprises both a capacitor insulator and a gate insulator. In addition, after forming the sidewall spacers, the invention dopes source and drain regions in the substrate.